In a design flow for an integrated circuit (IC) chip, static timing analysis for estimating delays in electronic circuits is employed in various stages to, for example, verify correct operations and optimize performance of the IC chip design. One factor that affects accuracy of delay calculation in static timing analysis is the resemblance of a predetermined input waveform used to characterize a cell for delay calculation to a propagated input waveform to the cell in a circuit which static timing analysis is performed on. However, as technology progresses, effects of, for example, increased length in interconnects for circuit connection and increased Miller capacitance in miniaturized transistors and non-planner transistors cause distortion in the propagated input waveform with respect to the predetermined input waveform. When the distortion in the propagated input waveform is ignored, accuracy in delay calculation is compromised.
Like reference symbols in the various drawings indicate like elements.